1. Field of the Invention
The invention relates in general to an integer frequency divider and a programmable integer frequency divider, and more particularly to an integer frequency divider and a programmable integer frequency divider capable of achieving a 50% duty cycle.
2. Description of the Related Art
In a common electronic circuit, different elements need to refer to a reference signal to perform individual or synchronous operations. The reference clock is usually generated by a frequency synthesizer according to a source clock. A frequency synthesizer usually includes a single-modulus or multi-modulus integer frequency divider. The integer frequency divider generates a low-frequency output signal according to a high-frequency input signal to provide an integer or fractional frequency dividing effect for subsequent uses. The fractional frequency dividing may be realized through a triangle integrator that controls an integer frequency divider operable with multiple divisors.
Implementation of the foregoing integer frequency divider may be achieved by a latch or multiple latches connected in series. The latch/latches generate(s) an output clock having a frequency that is (1/K) of an input clock, where K is a frequency divisor of the integer frequency divider. To ensure that the output clock provides sufficient and equal high-level and low-level periods for later uses, an ideal duty cycle of the output clock is 50%. However, when K is a non-integral multiple of 2 (e.g., when K is equal to 3), in order to generate an output signal having a 50% duty cycle, the integer frequency divider requires an additional control/trimming circuit or the latch/latches require(s) an additional control signal θ. The additional control/trimming circuit or control signal θ consumes more costs, limits the operation speed of the overall circuit, and/or increases control complications. Further, a latch suitable for an even divisor is not suitable in operations of a latch for an odd divisor. As a result, a programmable integer frequency divider implemented by latches cannot at the same time support odd-number and even-number frequency dividing operations, thus posing substantial limitations on the application of the programmable integer frequency divider. Prior art of the technical field may be referred from Taiwan Patent Publication 200816639; U.S. Pat. No. 6,123,796; and following periodicals: Rahul Magoon et al., “A Single-Chip Quad-Band (950/1000/1900/11000 MHz) Direct Conversion GSM/GPRS RF Transceiver with Integrated VCOs and Fractional-N Synthesizer,” in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002; Sheng-Che Tseng et al., “True 50% Duty-Cycle SSH and SHH SiGe BiCMOS Divide-by-3 Prescalers,” in IEICE TRANS. ELECTRON., VOL. E-89-C, NO. 6 Jun. 2006.